Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
142
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
16.4
Functional Description
The Periodic Interval Timer aims at providing periodic interrupts for use by operating systems.
The PIT provides a programmable overflow counter and a reset-on-read feature. It is built around two counters: a 20-bit
CPIV counter and a 12-bit PICNT counter. Both counters work at Master Clock /16.
CPIV counter and a 12-bit PICNT counter. Both counters work at Master Clock /16.
The first 20-bit CPIV counter increments from 0 up to a programmable overflow value set in the field PIV of the Mode
Register (PIT_MR). When the counter CPIV reaches this value, it resets to 0 and increments the Periodic Interval
Counter, PICNT. The status bit PITS in the Status Register (PIT_SR) rises and triggers an interrupt, provided the
interrupt is enabled (PITIEN in PIT_MR).
Register (PIT_MR). When the counter CPIV reaches this value, it resets to 0 and increments the Periodic Interval
Counter, PICNT. The status bit PITS in the Status Register (PIT_SR) rises and triggers an interrupt, provided the
interrupt is enabled (PITIEN in PIT_MR).
Writing a new PIV value in PIT_MR does not reset/restart the counters.
When CPIV and PICNT values are obtained by reading the Periodic Interval Value Register (PIT_PIVR), the overflow
counter (PICNT) is reset and the PITS is cleared, thus acknowledging the interrupt. The value of PICNT gives the
number of periodic intervals elapsed since the last read of PIT_PIVR.
counter (PICNT) is reset and the PITS is cleared, thus acknowledging the interrupt. The value of PICNT gives the
number of periodic intervals elapsed since the last read of PIT_PIVR.
When CPIV and PICNT values are obtained by reading the Periodic Interval Image Register (PIT_PIIR), there is no effect
on the counters CPIV and PICNT, nor on the bit PITS. For example, a profiler can read PIT_PIIR without clearing any
pending interrupt, whereas a timer interrupt clears the interrupt by reading PIT_PIVR.
on the counters CPIV and PICNT, nor on the bit PITS. For example, a profiler can read PIT_PIIR without clearing any
pending interrupt, whereas a timer interrupt clears the interrupt by reading PIT_PIVR.
The PIT may be enabled/disabled using the PITEN bit in the PIT_MR register (disabled on reset). The PITEN bit only
becomes effective when the CPIV value is 0.
becomes effective when the CPIV value is 0.
illustrates the PIT counting. After the PIT Enable bit is reset
(PITEN= 0), the CPIV goes on counting until the PIV value is reached, and is then reset. PIT restarts counting, only if the
PITEN is set again.
PITEN is set again.
The PIT is stopped when the core enters debug state.
Figure 16-2. Enabling/Disabling PIT with PITEN
MCK Prescaler
PIV
PIV - 1
0
PITEN
1
0
0
15
CPIV
1
restarts MCK Prescaler
0
1
APB cycle
read PIT_PIVR
0
PICNT
PITS (PIT_SR)
MCK
APB Interface
APB cycle