Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
25
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
6.1
Memory Mapping
A first level of address decoding is performed by the AHB Bus Matrix, i.e., the implementation of the Advanced High
performance Bus (AHB) for its Master and Slave interfaces with additional features.
performance Bus (AHB) for its Master and Slave interfaces with additional features.
Decoding breaks up the 4 Gbytes of address space into 16 banks of 256 Mbytes. The banks 1 to 6 are directed to the EBI
that associates these banks to the external chip selects EBI_NCS0 to EBI_NCS5. The bank 0 is reserved for the
addressing of the internal memories, and a second level of decoding provides 1Mbyte of internal memory area. Bank 15
is reserved for the peripherals and provides access to the Advanced Peripheral Bus (APB).
that associates these banks to the external chip selects EBI_NCS0 to EBI_NCS5. The bank 0 is reserved for the
addressing of the internal memories, and a second level of decoding provides 1Mbyte of internal memory area. Bank 15
is reserved for the peripherals and provides access to the Advanced Peripheral Bus (APB).
Other areas are unused and performing an access within them provides an abort to the master requesting such an
access.
access.
6.2
Embedded Memories
6.2.1 Internal
SRAM
The SAM9N12/CN11/CN12 embeds a total of 32 Kbytes high-speed SRAM.
After reset and until the Remap Command is performed, the SRAM is only accessible at address 0x0030 0000.
After Remap, the SRAM also becomes available at address 0x0.
6.2.2 Internal
ROM
The SAM9CN12 contains the secure bootloader (standard bootloader for SAM9N12 and SAM9CN11) and specific tables
used to compute SLC and MLC NAND Flash ECC.
used to compute SLC and MLC NAND Flash ECC.
The ROM is mapped at address 0x0010 0000. It is also accessible at address 0x0 (BMS = 1) after the reset and before
the Remap Command.
the Remap Command.
6.3
External Memories Overview
The SAM9N12/CN11/CN12 features an External Bus Interface to provide interface to a wide range of external memories
and to any parallel peripheral.
and to any parallel peripheral.
6.3.1
External Bus Interface
Integrates three External Memory Controllers:
Static Memory Controller
DDR2/SDRAM Controller
MLC NAND Flash ECC Controller
Up to 26-bit Address Bus (up to 64 MBytes linear per chip select)
Up to 6 chips selects, Configurable Assignment:
Static Memory Controller on NCS0, NCS1, NCS2, NCS3, NCS4, NCS5
DDR2/SDRAM Controller (SDCS) or Static Memory Controller on NCS1
NAND Flash support on NCS3
6.3.2
Static Memory Controller
8- or 16-bit Data Bus
Multiple Access Modes supported
Byte Write or Byte Select Lines
Asynchronous read in Page Mode supported (4- up to 16-byte page size)
Multiple device adaptability
Control signals programmable setup, pulse and hold time for each Memory Bank
Multiple Wait State Management