Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

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SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

The Debug Unit features two chip identifier registers, DBGU_CIDR (Chip ID Register) and DBGU_EXID (Extension ID).
Both registers contain a hard-wired value that is read-only. The first register contains the following fields:

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EXT - shows the use of the extension identifier register

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NVPTYP and NVPSIZ - identifies the type of embedded non-volatile memory and its size

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ARCH - identifies the set of embedded peripherals

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SRAMSIZ - indicates the size of the embedded SRAM

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EPROC - indicates the embedded ARM processor 

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VERSION - gives the revision of the silicon

The second register is device-dependent and reads 0 if the bit EXT is 0.

The Debug Unit allows blockage of access to the system through the ARM processor's ICE interface. This feature is
implemented via the register Force NTRST (DBGU_FNR), that allows assertion of the NTRST signal of the ICE Interface.
Writing the bit FNTRST (Force NTRST) to 1 in this register prevents any activity on the TAP controller. 

On standard devices, the bit FNTRST resets to 0 and thus does not prevent ICE access. 

This feature is especially useful on custom ROM devices for customers who do not want their on-chip code to be visible.