Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

Product codes
AT91SAM9N12-EK
Page of 1104
286
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
Figure 25-3.  Fuse Write
25.4.3 Fuse 
Masking
It is possible to mask the first 8 FUSE_SRx registers so that they will be read at a value of “0”, regardless of the fuse
state.
To activate fuse masking on the first 8 FUSE_SRx registers, the MSK bit of the Fuse Mode register (FUSE_MR) must be
written to level “1”. The MSK bit is write-only. Solely a general reset can disable fuse masking.
00
XX
XX
Fuse[31:0]
Fuse[63:32]
01
Clock
WSEL
DATA
WRQ
WS
RS