Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
315
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
27.6
Product Dependencies
27.6.1 I/O
Lines
The pins used for interfacing the External Bus Interface may be multiplexed with the PIO lines. The programmer must
first program the PIO controller to assign the External Bus Interface pins to their peripheral function. If I/O lines of the
External Bus Interface are not used by the application, they can be used for other purposes by the PIO Controller.
first program the PIO controller to assign the External Bus Interface pins to their peripheral function. If I/O lines of the
External Bus Interface are not used by the application, they can be used for other purposes by the PIO Controller.
27.7
Functional Description
The EBI transfers data between the internal AHB Bus (handled by the Bus Matrix) and the external memories or
peripheral devices. It controls the waveforms and the parameters of the external address, data and control buses and is
composed of the following elements:
peripheral devices. It controls the waveforms and the parameters of the external address, data and control buses and is
composed of the following elements:
the Static Memory Controller (SMC)
the DDR2/SDRAM Controller (DDR2SDRC)
the Programmable Multi-bit ECC Controller (PMECC)
a chip select assignment feature that assigns an AHB address space to the external devices
a multiplex controller circuit that shares the pins between the different Memory Controllers
programmable NAND Flash support logic
27.7.1 Bus
Multiplexing
The EBI offers a complete set of control signals that share the 32-bit data lines, the address lines of up to 26 bits and the
control signals through a multiplex logic operating in function of the memory area requests.
control signals through a multiplex logic operating in function of the memory area requests.
Multiplexing is specifically organized in order to guarantee the maintenance of the address and output control lines at a
stable state while no external access is being performed. Multiplexing is also designed to respect the data float times
defined in the Memory Controllers. Furthermore, refresh cycles of the DDR2 and SDRAM are executed independently by
the DDR2SDR Controller without delaying the other external Memory Controller accesses.
stable state while no external access is being performed. Multiplexing is also designed to respect the data float times
defined in the Memory Controllers. Furthermore, refresh cycles of the DDR2 and SDRAM are executed independently by
the DDR2SDR Controller without delaying the other external Memory Controller accesses.
27.7.2 Pull-up
Control
The EBI_CSA registers in the Chip Configuration User Interface permit enabling of on-chip pull-up resistors on the data
bus lines not multiplexed with the PIO Controller lines. The pull-up resistors are enabled after reset. Setting the
EBIx_DBPUC bit disables the pull-up resistors on the D0 to D15 lines. Enabling the pull-up resistor on the D16-D31 lines
can be performed by programming the appropriate PIO controller.
bus lines not multiplexed with the PIO Controller lines. The pull-up resistors are enabled after reset. Setting the
EBIx_DBPUC bit disables the pull-up resistors on the D0 to D15 lines. Enabling the pull-up resistor on the D16-D31 lines
can be performed by programming the appropriate PIO controller.
27.7.3 Drive
level
The EBI I/Os accept two drive level, HIGH and LOW. This allows to avoid overshoots and give the best performances
according to the bus load and external memories.
according to the bus load and external memories.
The voltage ranges and the slew rates are determined by programming EBI_DRIVE field in the Chip Configuration
registers located in the Matrix User Interface.
registers located in the Matrix User Interface.
At reset the selected current drive is HIGH.