Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
348
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
28.6.5 PMECC Clock Control Register
Name:
PMECC_CLK
Address:
0xFFFFE010
Access:
Read-write
Reset:
0x00000000
• CLKCTRL: Clock Control Register
The PMECC Module data path Setup Time is set to CLKCTRL+1.
This field indicates the database setup times in number of clock cycles. At 133 Mhz, this field must be programmed with 2, indicat-
ing that the setup time is 3 clock cycles.
ing that the setup time is 3 clock cycles.
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
7
6
5
4
3
2
1
0
–
–
–
–
–
CLKCTRL