Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

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SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

The ARM9EJ-S processor can operate in three different states, each with a specific instruction set:



ARM state: 32-bit, word-aligned ARM instructions.

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THUMB state: 16-bit, halfword-aligned Thumb instructions.

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Jazelle state: variable length, byte-aligned Jazelle instructions.

In Jazelle state, all instruction Fetches are in words.

The operating state of the ARM9EJ-S core can be switched between:



ARM state and THUMB state using the BX and BLX instructions, and loads to the PC 



ARM state and Jazelle state using the BXJ instruction 

All exceptions are entered, handled and exited in ARM state. If an exception occurs in Thumb or Jazelle states, the
processor reverts to ARM state. The transition back to Thumb or Jazelle states occurs automatically on return from the
exception handler.

The ARM9EJ-S core uses two kinds of pipelines to increase the speed of the flow of instructions to the processor. 

A five-stage (five clock cycles) pipeline is used for ARM and Thumb states. It consists of Fetch, Decode, Execute,
Memory and Writeback stages.

A six-stage (six clock cycles) pipeline is used for Jazelle state It consists of Fetch, Jazelle/Decode (two clock cycles),
Execute, Memory and Writeback stages. 

The ARM9EJ-S core supports byte (8-bit), half-word (16-bit) and word (32-bit) access. Words must be aligned to four-
byte boundaries, half-words must be aligned to two-byte boundaries and bytes can be placed on any byte boundary.

Because of the nature of the pipelines, it is possible for a value to be required for use before it has been placed in the
register bank by the actions of an earlier instruction. The ARM9EJ-S control logic automatically detects these cases and
stalls the core or forward data.

The Jazelle technology enables direct and efficient execution of Java byte codes on ARM processors, providing high
performance for the next generation of Java-powered wireless and embedded devices.

The new Java feature of ARM9EJ-S can be described as a hardware emulation of a JVM (Java Virtual Machine). Java
mode will appear as another state: instead of executing ARM or Thumb instructions, it executes Java byte codes. The
Java byte code decoder logic implemented in ARM9EJ-S decodes 95% of executed byte codes and turns them into ARM
instructions without any overhead, while less frequently used byte codes are broken down into optimized sequences of
ARM instructions. The hardware/software split is invisible to the programmer, invisible to the application and invisible to
the operating system. All existing ARM registers are re-used in Jazelle state and all registers then have particular
functions in this mode.

Minimum interrupt latency is maintained across both ARM state and Java state. Since byte codes execution can be
restarted, an interrupt automatically triggers the core to switch from Java state to ARM state for the execution of the
interrupt handler. This means that no special provision has to be made for handling interrupts while executing byte
codes, whether in hardware or in software.