Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
400
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
30.13 Slow Clock Mode
The SMC is able to automatically apply a set of “slow clock mode” read/write waveforms when an internal signal driven
by the Power Management Controller is asserted because MCK has been turned to a very slow clock rate (typically
32kHz clock rate). In this mode, the user-programmed waveforms are ignored and the slow clock mode waveforms are
applied. This mode is provided so as to avoid reprogramming the User Interface with appropriate waveforms at very slow
clock rate. When activated, the slow mode is active on all chip selects.
by the Power Management Controller is asserted because MCK has been turned to a very slow clock rate (typically
32kHz clock rate). In this mode, the user-programmed waveforms are ignored and the slow clock mode waveforms are
applied. This mode is provided so as to avoid reprogramming the User Interface with appropriate waveforms at very slow
clock rate. When activated, the slow mode is active on all chip selects.
30.13.1 Slow Clock Mode Waveforms
illustrates the read and write operations in slow clock mode. They are valid on all chip selects.
indicates the value of read and write parameters in slow clock mode.
Figure 30-31. Read/write Cycles in Slow Clock Mode
A[
25:2]
NCS
1
MCK
NWE
1
1
NWE_CYCLE = 3
A
[25:2]
MCK
NRD
NRD_CYCLE = 2
1
1
NCS
SLOW CLOCK MODE WRITE
SLOW CLOCK MODE READ
NBS0, NBS1,
NBS2, NBS3,
A0,A1
NBS2, NBS3,
A0,A1
NBS0, NBS1,
NBS2, NBS3,
A0,A1
NBS2, NBS3,
A0,A1
Table 30-5. Read and Write Timing Parameters in Slow Clock Mode
Read Parameters
Duration (cycles)
Write Parameters
Duration (cycles)
NRD_SETUP
1
NWE_SETUP
1
NRD_PULSE
1
NWE_PULSE
1
NCS_RD_SETUP
0
NCS_WR_SETUP
0
NCS_RD_PULSE
2
NCS_WR_PULSE
3
NRD_CYCLE
2
NWE_CYCLE
3