Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
409
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
30.16.3 SMC Cycle Register
Name:
SMC_CYCLE[0..
5
]
Addresses:
0xFFFFEA08 [0], 0xFFFFEA18 [1], 0xFFFFEA28 [2], 0xFFFFEA38 [3], 0xFFFFEA48 [4], 0xFFFFEA58 [5]
Access:
Read-write
• NWE_CYCLE: Total Write Cycle Length
The total write cycle length is the total duration in clock cycles of the write cycle. It is equal to the sum of the setup, pulse and hold
steps of the NWE and NCS signals. It is defined as:
steps of the NWE and NCS signals. It is defined as:
Write cycle length = (NWE_CYCLE[8:7]*256 + NWE_CYCLE[6:0]) clock cycles
• NRD_CYCLE: Total Read Cycle Length
The total read cycle length is the total duration in clock cycles of the read cycle. It is equal to the sum of the setup, pulse and hold
steps of the NRD and NCS signals. It is defined as:
steps of the NRD and NCS signals. It is defined as:
Read cycle length = (NRD_CYCLE[8:7]*256 + NRD_CYCLE[6:0]) clock cycles
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
NRD_CYCLE
23
22
21
20
19
18
17
16
NRD_CYCLE
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
NWE_CYCLE
7
6
5
4
3
2
1
0
NWE_CYCLE