Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
449
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
31.7.4 DDRSDRC Timing Parameter 0 Register
Name:
DDRSDRC_TPR0
Address:
0xFFFFE80C
Access:
Read-write
Reset:
See
This register can only be written if the WPEN bit is cleared in
.
• TRAS: Active to Precharge Delay
Reset Value is 5 cycles.
This field defines the delay between an Activate Command and a Precharge Command in number of cycles. Number of cycles is
between 0 and 15.
between 0 and 15.
• TRCD: Row to Column Delay
Reset Value is 2 cycles.
This field defines the delay between an Activate Command and a Read/Write Command in number of cycles. Number of cycles is
between 0 and 15.
between 0 and 15.
• TWR: Write Recovery Delay
Reset value is 2 cycles.
This field defines the Write Recovery Time in number of cycles. Number of cycles is between 1 and 15.
• TRC: Row Cycle Delay
Reset value is 7 cycles.
This field defines the delay between an Activate command and Refresh command in number of cycles. Number of cycles is
between 0 and 15
between 0 and 15
• TRP: Row Precharge Delay
Reset Value is 2 cycles.
This field defines the delay between a Precharge Command and another command in number of cycles. Number of cycles is
between 0 and 15.
between 0 and 15.
• TRRD: Active bankA to Active bankB
Reset value is 2 cycles.
This field defines the delay between an Active command in BankA and an active command in bankB in number of cycles. Number
of cycles is between 1 and 15.
of cycles is between 1 and 15.
31
30
29
28
27
26
25
24
TMRD
REDUCE_WRRD
TWTR
23
22
21
20
19
18
17
16
TRRD
TRP
15
14
13
12
11
10
9
8
TRC
TWR
7
6
5
4
3
2
1
0
TRCD
TRAS