Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
452
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
31.7.6 DDRSDRC Timing Parameter 2 Register
Name:
DDRSDRC_TPR2
Address:
0xFFFFE814
Access:
Read-write
Reset:
See
This register can only be written if the WPEN bit is cleared in
.
• TXARD: Exit Active Power Down Delay to Read Command in Mode “Fast Exit”.
The Reset Value is 2 cycles.
This field defines the delay between cke set high and a Read Command in number of cycles. Number of cycles is between 0 and
15.
15.
Note:
This field is found only in DDR2-SDRAM devices.
• TXARDS: Exit Active Power Down Delay to Read Command in Mode “Slow Exit”.
The Reset Value is 6 cycles.
This field defines the delay between cke set high and a Read Command in number of cycles. Number of cycles is between 0 and
15.
15.
Note:
This field is found only in DDR2-SDRAM devices.
• TRPA: Row Precharge All Delay
The Reset Value is 0 cycle.
This field defines the delay between a Precharge ALL banks Command and another command in number of cycles. Number of
cycles is between 0 and 15.
cycles is between 0 and 15.
Note:
This field is found only in DDR2-SDRAM devices.
• TRTP: Read to Precharge
The Reset Value is 2 cycles.
This field defines the delay between Read Command and a Precharge command in number of cycle.
Number of cycles is between 0 and 7.
• TFAW: Four Active Window
The Reset Value is 4 cycles.
DDR2 devices with 8-banks (1Gb or larger) have an additional requirement: t
FAW
. This requires that no more than four
ACTIVATE commands may be issued in any given t
FAW
(MIN) period.
Number of cycles is between 0 and 15.
Note:
This field is found only in DDR-SDRAM 2 devices with eight internal banks
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
TFAW
15
14
13
12
11
10
9
8
TRTP
TRPA
7
6
5
4
3
2
1
0
TXARDS
TXARD