Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
503
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
32.8.13 DMAC Channel x [x = 0..7] Source Address Register
Name:
DMAC_SADDRx [x = 0..7]
Addresses:
0xFFFFEC3C [0], 0xFFFFEC64 [1], 0xFFFFEC8C [2], 0xFFFFECB4 [3], 0xFFFFECDC [4], 0xFFFFED04 [5],
0xFFFFED2C [6], 0xFFFFED54 [7]
0xFFFFED2C [6], 0xFFFFED54 [7]
Access: Read-write
Reset: 0x00000000
This register can only be written if the WPEN bit is cleared in
• SADDR: Channel x Source Address
This register must be aligned with the source transfer width.
31
30
29
28
27
26
25
24
SADDR
23
22
21
20
19
18
17
16
SADDR
15
14
13
12
11
10
9
8
SADDR
7
6
5
4
3
2
1
0
SADDR