Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
506
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
32.8.16 DMAC Channel x [x = 0..7] Control A Register
Name:
DMAC_CTRLAx [x = 0..7]
Addresses:
0xFFFFEC48 [0], 0xFFFFEC70 [1], 0xFFFFEC98 [2], 0xFFFFECC0 [3], 0xFFFFECE8 [4], 0xFFFFED10 [5],
0xFFFFED38 [6], 0xFFFFED60 [7]
0xFFFFED38 [6], 0xFFFFED60 [7]
Access:
Read-write
Reset: 0x00000000
This register can only be written if the WPEN bit is cleared in
• BTSIZE: Buffer Transfer Size
The transfer size relates to the number of transfers to be performed, that is, for writes it refers to the number of source width trans-
fers to perform when DMAC is flow controller. For Reads, BTSIZE refers to the number of transfers completed on the Source
Interface. When this field is set to 0, the DMAC module is automatically disabled when the relevant channel is enabled.
fers to perform when DMAC is flow controller. For Reads, BTSIZE refers to the number of transfers completed on the Source
Interface. When this field is set to 0, the DMAC module is automatically disabled when the relevant channel is enabled.
• SCSIZE: Source Chunk Transfer Size.
• DCSIZE: Destination Chunk Transfer Size
31
30
29
28
27
26
25
24
DONE
–
DST_WIDTH
–
–
SRC_WIDTH
23
22
21
20
19
18
17
16
–
DCSIZE
–
SCSIZE
15
14
13
12
11
10
9
8
BTSIZE
7
6
5
4
3
2
1
0
BTSIZE
Value
Name
Description
000
CHK_1
1 data transferred
001
CHK_4
4 data transferred
010
CHK_8
8 data transferred
011
CHK_16
16 data transferred
100
CHK_32
32 data transferred
101
CHK_64
64 data transferred
110
CHK_128
128 data transferred
111
CHK_256
256 data transferred
Value
Name
Description
000
CHK_1
1 data transferred
001
CHK_4
4 data transferred
010
CHK_8
8 data transferred
011
CHK_16
16 data transferred
100
CHK_32
32 data transferred