Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

545

SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

UDP_CSRx [x = 0..5]

0xF803C030

Read-write 

WARNING: Due to synchronization between MCK and UDPCK, the software application must wait for the end of the write opera-
tion before executing another write by polling the bits which must be set/cleared.

#if defined ( __ICCARM__ )

  #define nop() (__no_operation())

#elif defined   (  __GNUC__  )

  #define nop()   __asm__ __volatile__ ( "nop" )

#endif

/// Bitmap for all status bits in CSR that are not effected by a value 1.

#define REG_NO_EFFECT_1_ALL

AT91C_UDP_RX_DATA_BK0\

| AT91C_UDP_RX_DATA_BK1\

| AT91C_UDP_STALLSENT\

| AT91C_UDP_RXSETUP\

| AT91C_UDP_TXCOMP

/// Sets the specified bit(s) in the UDP_CSR register.

/// \param endpoint The endpoint number of the CSR to process.

/// \param flags The bitmap to set to 1.

#define SET_CSR(endpoint, flags) \

   { \

       volatile unsigned int reg; \

       reg = AT91C_BASE_UDP->UDP_CSR[endpoint] ; \

       reg |= REG_NO_EFFECT_1_ALL; \

       reg |= (flags); \

       AT91C_BASE_UDP->UDP_CSR[endpoint] = reg; \

for( nop_count=0; nop_count<15; nop_count++ ) {\

                nop();\

        }\

    }

31

30

29

28

27

26

25

24

–

–

–

–

–

RXBYTECNT

23

22

21

20

19

18

17

16

RXBYTECNT

15

14

13

12

11

10

9

8

EPEDS

–

–

–

DTGLE

EPTYPE

7

6

5

4

3

2

1

0

DIR

RX_DATA_BK1 FORCESTALL

TXPKTRDY

STALLSENT

RXSETUP

RX_DATA_ 

BK0

TXCOMP