Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
558
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
34.4
Product Dependencies
34.4.1 I/O
Lines
DPs and DMs are not controlled by any PIO controllers. The embedded USB physical transceivers are controlled by the
USB host controller.
USB host controller.
34.4.2 Power
Management
The USB host controller requires a 48 MHz clock. This clock must be generated by a PLL with a correct accuracy
of ± 0.25%.
of ± 0.25%.
Thus the USB device peripheral receives two clocks from the Power Management Controller (PMC): the master clock
MCK used to drive the peripheral user interface (MCK domain) and the UHPCLK 48 MHz clock used to interface with the
bus USB signals (Recovered 12 MHz domain).
MCK used to drive the peripheral user interface (MCK domain) and the UHPCLK 48 MHz clock used to interface with the
bus USB signals (Recovered 12 MHz domain).
34.4.3 Interrupt
The USB host interface has an interrupt line connected to the Advanced Interrupt Controller (AIC).
Handling USB host interrupts requires programming the AIC before configuring the UHP.