Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

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SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

In write operation, the HSMCI Mode Register (HSMCI_MR) is used to define the padding value when writing non-multiple
block size. If the bit PADV is 0, then 0x00 value is used when padding data, otherwise 0xFF is used.

If set, the bit DMAEN in the HSMCI_DMA register enables DMA transfer.

The following flowchart (

) shows how to write a single block with or without use of DMA facilities. Polling or

interrupt method can be used to wait for the end of write according to the contents of the Interrupt Mask Register
(HSMCI_IMR).