Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

592

SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

Name: HSMCI_DTOR

0xF0008008

Access: Read/Write 

 

This register can only be written if the WPEN bit is cleared in 

.

This field determines the maximum number of Master Clock cycles that the HSMCI waits between two data block transfers. It 
equals (DTOCYC x Multiplier).

Multiplier is defined by DTOMUL as shown in the following table:

If the data time-out set by DTOCYC and DTOMUL has been exceeded, the Data Time-out Error flag (DTOE) in the HSMCI Status 
Register (HSMCI_SR) rises.

31

30

29

28

27

26

25

24

–

–

–

–

–

–

–

–

23

22

21

20

19

18

17

16

–

–

–

–

–

–

–

–

15

14

13

12

11

10

9

8

–

–

–

–

–

–

–

–

7

6

5

4

3

2

1

0

–

DTOMUL

DTOCYC

0

1

DTOCYC

1

16

DTOCYC x 16

2

128

DTOCYC x 128

3

256

DTOCYC x 256

4

1024

DTOCYC x 1024

5

4096

DTOCYC x 4096

6

65536

DTOCYC x 65536

7

1048576

DTOCYC x 1048576