Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

612

SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

Name: HSMCI_CFG

0xF0008054

Access: Read/Write

This register can only be written if the WPEN bit is cleared in 

.

0: A write transfer starts when a sufficient amount of data is written into the FIFO.

When the block length is greater than or equal to 3/4 of the HSMCI internal FIFO size, then the write transfer starts as soon as 
half the FIFO is filled. When the block length is greater than or equal to half the internal FIFO size, then the write transfer starts as 
soon as one quarter of the FIFO is filled. In other cases, the transfer starts as soon as the total amount of data is written in the 
internal FIFO.

1: A write transfer starts as soon as one data is written into the FIFO.

0: When an underflow/overflow condition flag is set, a new Write/Read command is needed to reset the flag.

1: When an underflow/overflow condition flag is set, a read status resets the flag.

0: Default bus timing mode.

1: If set to one, the host controller outputs command line and data lines on the rising edge of the card clock. The Host driver shall 
check the high speed support in the card registers.

0: The pending command is sent at the end of the current data block.

1: The pending command is sent at the end of the block transfer when the transfer length is not infinite (block count shall be differ-
ent from zero).

31

30

29

28

27

26

25

24

–

–

–

–

–

–

–

–

23

22

21

20

19

18

17

16

–

–

–

–

–

–

–

–

15

14

13

12

11

10

9

8

–

–

–

LSYNC

–

–

–

HSMODE

7

6

5

4

3

2

1

0

–

–

–

FERRCTRL

–

–

–

FIFOMODE