Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
625
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
shows Transmit Data Register Empty (TDRE), Receive Data Register (RDRF) and Transmission Register
Empty (TXEMPTY) status flags behavior within the SPI_SR (Status Register) during an 8-bit data transfer in fixed mode
and no Peripheral Data Controller involved.
and no Peripheral Data Controller involved.
Figure 36-7. Status Register Flags Behavior
36.7.3.3 Clock Generation
The SPI Baud rate clock is generated by dividing the Master Clock (MCK), by a value between 1 and 255.
This allows a maximum operating baud rate at up to Master Clock and a minimum operating baud rate of MCK divided by
255.
255.
Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead to unpredictable results.
At reset, SCBR is 0 and the user has to program it at a valid value before performing the first transfer.
The divisor can be defined independently for each chip select, as it has to be programmed in the SCBR field of the Chip
Select Registers. This allows the SPI to automatically adapt the baud rate for each interfaced peripheral without
reprogramming.
Select Registers. This allows the SPI to automatically adapt the baud rate for each interfaced peripheral without
reprogramming.
36.7.3.4 Transfer Delays
shows a chip select transfer change and consecutive transfers on the same chip select. Three delays can be
programmed to modify the transfer waveforms:
The delay between chip selects, programmable only once for all the chip selects by writing the DLYBCS field in the
Mode Register. Allows insertion of a delay between release of one chip select and before assertion of a new one.
Mode Register. Allows insertion of a delay between release of one chip select and before assertion of a new one.
The delay before SPCK, independently programmable for each chip select by writing the field DLYBS. Allows the
start of SPCK to be delayed after the chip select has been asserted.
start of SPCK to be delayed after the chip select has been asserted.
The delay between consecutive transfers, independently programmable for each chip select by writing the
DLYBCT field. Allows insertion of a delay between two transfers occurring on the same chip select
DLYBCT field. Allows insertion of a delay between two transfers occurring on the same chip select
These delays allow the SPI to be adapted to the interfaced peripherals and their speed and bus release time.
6
SPCK
MOSI
(from master)
MISO
(from slave)
NPCS0
MSB
MSB
LSB
LSB
6
6
5
5
4
4
3
3
2
2
1
1
1
2
3
4
5
7
8
6
RDRF
TDRE
TXEMPTY
Write in
SPI_TDR
RDR read
shift register empty