Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

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SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

The interrupt source 0 is the only source which can raise a fast interrupt request to the processor except if fast forcing is
used. The interrupt source 0 is generally connected to a FIQ pin of the product, either directly or through a PIO
Controller. 

The fast interrupt logic of the AIC has no priority controller. The mode of interrupt source 0 is programmed with the
AIC_SMR0 and the field PRIOR of this register is not used even if it reads what has been written. The field SRCTYPE of
AIC_SMR0 enables programming the fast interrupt source to be positive-edge triggered or negative-edge triggered or
high-level sensitive or low-level sensitive

Writing 0x1 in the AIC_IECR (Interrupt Enable Command Register) and AIC_IDCR (Interrupt Disable Command
Register) respectively enables and disables the fast interrupt. The bit 0 of AIC_IMR (Interrupt Mask Register) indicates
whether the fast interrupt is enabled or disabled.

The fast interrupt handler address can be stored in AIC_SVR0 (Source Vector Register 0). The value written into this
register is returned when the processor reads AIC_FVR (Fast Vector Register). This offers a way to branch in one single
instruction to the interrupt handler, as AIC_FVR is mapped at the absolute address 0xFFFF F104 and thus accessible
from the ARM fast interrupt vector at address 0x0000 001C through the following instruction: 

LDR

PC,[PC,# -&F20]

When the processor executes this instruction it loads the value read in AIC_FVR in its program counter, thus branching
the execution on the fast interrupt handler. It also automatically performs the clear of the fast interrupt source if it is
programmed in edge-triggered mode. 

This section gives an overview of the fast interrupt handling sequence when using the AIC. It is assumed that the
programmer understands the architecture of the ARM processor, and especially the processor interrupt modes and
associated status bits.

Assuming that:

1.

The Advanced Interrupt Controller has been programmed, AIC_SVR0 is loaded with the fast interrupt service rou-
tine address, and the interrupt source 0 is enabled.

2.

The Instruction at address 0x1C (FIQ exception vector address) is required to vector the fast interrupt:

LDR PC, [PC, # -&F20] 

3.

The user does not need nested fast interrupts.

When nFIQ is asserted, if the bit “F” of CPSR is 0, the sequence is:

1.

The CPSR is stored in SPSR_fiq, the current value of the program counter is loaded in the FIQ link register 
(R14_FIQ) and the program counter (R15) is loaded with 0x1C. In the following cycle, during fetch at address 
0x20, the ARM core adjusts R14_fiq, decrementing it by four.

2.

The ARM core enters FIQ mode.

3.

When the instruction loaded at address 0x1C is executed, the program counter is loaded with the value read in 
AIC_FVR. Reading the AIC_FVR has effect of automatically clearing the fast interrupt, if it has been programmed 
to be edge triggered. In this case only, it de-asserts the nFIQ line on the processor.

4.

The previous step enables branching to the corresponding interrupt service routine. It is not necessary to save the 
link register R14_fiq and SPSR_fiq if nested fast interrupts are not needed.

5.

The Interrupt Handler can then proceed as required. It is not necessary to save registers R8 to R13 because FIQ 
mode has its own dedicated registers and the user R8 to R13 are banked. The other registers, R0 to R7, must be 
saved before being used, and restored at the end (before the next step). Note that if the fast interrupt is pro-
grammed to be level sensitive, the source of the interrupt must be cleared during this phase in order to de-assert 
the interrupt source 0.