Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
630
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
36.7.4 SPI
Slave
Mode
When operating in Slave Mode, the SPI processes data bits on the clock provided on the SPI clock pin (SPCK).
The SPI waits for NSS to go active before receiving the serial clock from an external master. When NSS falls, the clock is
validated on the serializer, which processes the number of bits defined by the BITS field of the Chip Select Register 0
(SPI_CSR0). These bits are processed following a phase and a polarity defined respectively by the NCPHA and CPOL
bits of the SPI_CSR0. Note that BITS, CPOL and NCPHA of the other Chip Select Registers have no effect when the SPI
is programmed in Slave Mode.
validated on the serializer, which processes the number of bits defined by the BITS field of the Chip Select Register 0
(SPI_CSR0). These bits are processed following a phase and a polarity defined respectively by the NCPHA and CPOL
bits of the SPI_CSR0. Note that BITS, CPOL and NCPHA of the other Chip Select Registers have no effect when the SPI
is programmed in Slave Mode.
The bits are shifted out on the MISO line and sampled on the MOSI line.
(For more information on BITS field, see also, the
below the register table;
.)
When all the bits are processed, the received data is transferred in the Receive Data Register and the RDRF bit rises. If
the SPI_RDR (Receive Data Register) has not been read before new data is received, the Overrun Error bit (OVRES) in
SPI_SR is set. As long as this flag is set, data is loaded in SPI_RDR. The user has to read the status register to clear the
OVRES bit.
the SPI_RDR (Receive Data Register) has not been read before new data is received, the Overrun Error bit (OVRES) in
SPI_SR is set. As long as this flag is set, data is loaded in SPI_RDR. The user has to read the status register to clear the
OVRES bit.
When a transfer starts, the data shifted out is the data present in the Shift Register. If no data has been written in the
Transmit Data Register (SPI_TDR), the last data received is transferred. If no data has been received since the last
reset, all bits are transmitted low, as the Shift Register resets at 0.
Transmit Data Register (SPI_TDR), the last data received is transferred. If no data has been received since the last
reset, all bits are transmitted low, as the Shift Register resets at 0.
When a first data is written in SPI_TDR, it is transferred immediately in the Shift Register and the TDRE bit rises. If new
data is written, it remains in SPI_TDR until a transfer occurs, i.e. NSS falls and there is a valid clock on the SPCK pin.
When the transfer occurs, the last data written in SPI_TDR is transferred in the Shift Register and the TDRE bit rises.
This enables frequent updates of critical variables with single transfers.
data is written, it remains in SPI_TDR until a transfer occurs, i.e. NSS falls and there is a valid clock on the SPCK pin.
When the transfer occurs, the last data written in SPI_TDR is transferred in the Shift Register and the TDRE bit rises.
This enables frequent updates of critical variables with single transfers.
Then, a new data is loaded in the Shift Register from the Transmit Data Register. In case no character is ready to be
transmitted, i.e. no character has been written in SPI_TDR since the last load from SPI_TDR to the Shift Register, the
SPI_TDR is retransmitted.
transmitted, i.e. no character has been written in SPI_TDR since the last load from SPI_TDR to the Shift Register, the
SPI_TDR is retransmitted.
Figure 36-11. Slave Mode Functional Block Diagram
Shift Register
SPCK
SPIENS
LSB
MSB
NSS
MOSI
SPI_RDR
RD
SPI
Clock
TDRE
SPI_TDR
TD
RDRF
OVRES
SPI_CSR0
CPOL
NCPHA
BITS
SPIEN
SPIDIS
MISO