Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

634

SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

Name: SPI_MR

0xF0000004 (0), 0xF0004004 (1)

Read-write 

This register can only be written if the WPEN bit is cleared in 

0 = SPI is in Slave mode. 

1 = SPI is in Master mode.

0 = Fixed Peripheral Select.

1 = Variable Peripheral Select.

0 = The chip selects are directly connected to a peripheral device.

1 = The four chip select lines are connected to a 4- to 16-bit decoder.

When PCSDEC equals one, up to 15 Chip Select signals can be generated with the four lines using an external 4- to 16-bit 
decoder. The Chip Select Registers define the characteristics of the 15 chip selects according to the following rules:

SPI_CSR0 defines peripheral chip select signals 0 to 3.

SPI_CSR1 defines peripheral chip select signals 4 to 7.

SPI_CSR2 defines peripheral chip select signals 8 to 11.

SPI_CSR3 defines peripheral chip select signals 12 to 14.

0 = Mode fault detection is enabled. 

1 = Mode fault detection is disabled.

0 = No Effect. In master mode, a transfer can be initiated whatever the state of the Receive Data Register is.

1 = In Master Mode, a transfer can start only if the Receive Data Register is empty, i.e. does not contain any unread data. This 
mode prevents overrun error in reception.

0 = Local loopback path disabled. 

1 = Local loopback path enabled 

LLB controls the local loopback on the data serializer for testing in Master Mode only. (MISO is internally connected on MOSI.)

31

30

29

28

27

26

25

24

DLYBCS

23

22

21

20

19

18

17

16

–

–

–

–

PCS

15

14

13

12

11

10

9

8

–

–

–

–

–

–

–

–

7

6

5

4

3

2

1

0

LLB

–

WDRBT

MODFDIS

–

PCSDEC

PS

MSTR