Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
662
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
37.7
Timer Counter (TC) User Interface
Notes: 1. Channel index ranges from 0 to 2.
2. Read-only if WAVE = 0.
Table 37-5. Register Mapping
Offset
Register
Name
Access
Reset
0x00 + channel * 0x40 + 0x00
Channel Control Register
TC_CCR
Write-only
–
0x00 + channel * 0x40 + 0x04
Channel Mode Register
TC_CMR
Read-write
0
0x00 + channel * 0x40 + 0x08
Reserved
0x00 + channel * 0x40 + 0x0C
Register AB
TC_RAB
Read-only
0
0x00 + channel * 0x40 + 0x10
Counter Value
TC_CV
Read-only
0
0x00 + channel * 0x40 + 0x14
Register A
TC_RA
Read-write
0
0x00 + channel * 0x40 + 0x18
Register B
TC_RB
Read-write
0
0x00 + channel * 0x40 + 0x1C
Register C
TC_RC
Read-write
0
0x00 + channel * 0x40 + 0x20
Status Register
TC_SR
Read-only
0
0x00 + channel * 0x40 + 0x24
Interrupt Enable Register
TC_IER
Write-only
–
0x00 + channel * 0x40 + 0x28
Interrupt Disable Register
TC_IDR
Write-only
–
0x00 + channel * 0x40 + 0x2C
Interrupt Mask Register
TC_IMR
Read-only
0
0xC0
Block Control Register
TC_BCR
Write-only
–
0xC4
Block Mode Register
TC_BMR
Read-write
0
0xC8 - 0xD4
Reserved
0xD8
Reserved
0xE4
Reserved
0xE8 - 0xFC
Reserved
–
–
–