Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
692
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
38.7.1 PWM
Mode
Register
Name:
PWM_MR
Address:
0xF8034000
Access:
Read/Write
• DIVA, DIVB: CLKA, CLKB Divide Factor
• PREA, PREB
Values which are not listed in the table must be considered as “reserved”.
31
30
29
28
27
26
25
24
–
–
–
–
PREB
23
22
21
20
19
18
17
16
DIVB
15
14
13
12
11
10
9
8
–
–
–
–
PREA
7
6
5
4
3
2
1
0
DIVA
Value
Name
Description
0
CLK_OFF
CLKA, CLKB clock is turned off
1
CLK_DIV1
CLKA, CLKB clock is clock selected by PREA, PREB
2-255
–
CLKA, CLKB clock is clock selected by PREA, PREB
divided by DIVA, DIVB factor.
divided by DIVA, DIVB factor.
Value
Name
Description
0000
MCK
Master Clock
0001
MCKDIV2
Master Clock divided by 2
0010
MCKDIV4
Master Clock divided by 4
0011
MCKDIV8
Master Clock divided by 8
0100
MCKDIV16
Master Clock divided by 16
0101
MCKDIV32
Master Clock divided by 32
0110
MCKDIV64
Master Clock divided by 64
0111
MCKDIV128
Master Clock divided by 128
1000
MCKDIV256
Master Clock divided by 256
1001
MCKDIV512
Master Clock divided by 512
1010
MCKDIV1024
Master Clock divided by 1024