Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

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SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

The following flowcharts shown in 

, 

,

 and 

 give examples for read and write operations. A polling or

interrupt method can be used to check the status bits. The interrupt method requires that the interrupt enable register
(TWI_IER) be configured first.

Set TWI clock

(CLDIV, CHDIV, CKDIV) in TWI_CWGR

(Needed only once)

Set the Control register:

- Master enable

TWI_CR = MSEN + SVDIS

Set the Master Mode register:

- Device slave address (DADR)

- Transfer direction bit

Write ==> bit MREAD = 0

Load Transmit register

TWI_THR = Data to send

Read Status register

TXRDY = 1?

Read Status register

TXCOMP = 1?

Transfer finished

Yes

Yes

BEGIN

No

No

Write STOP Command

TWI_CR = STOP