Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

727

SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

In the case of a Write sequence (SVREAD is low), the RXRDY (Receive Holding Register Ready) flag is set as soon as a
character has been received in the TWI_RHR (TWI Receive Holding Register). RXRDY is reset when reading the
TWI_RHR. 

TWI continues receiving data until a STOP condition or a REPEATED_START + an address different from SADR is
detected. Note that at the end of the write sequence TXCOMP flag is set and SVACC reset.

.

In the case where TWI_THR or TWI_RHR is not written/read in time, TWI performs a clock synchronization. 

Clock stretching information is given by the SCLWS (Clock Wait state) bit. 

 and 

In the case where a GENERAL CALL is performed, GACC (General Call ACCess) flag is set. 

After GACC is set, it is up to the programmer to interpret the meaning of the GENERAL CALL and to decode the new
address programming sequence. 

.

The read mode is defined as a data requirement from the master.

After a START or a REPEATED START condition is detected, the decoding of the address starts. If the slave address
(SADR) is decoded, SVACC is set and SVREAD indicates the direction of the transfer.

Until a STOP or REPEATED START condition is detected, TWI continues sending data loaded in the TWI_THR.

If a STOP condition or a REPEATED START + an address different from SADR is detected, SVACC is reset.

Notes: 1. When SVACC is low, the state of SVREAD becomes irrelevant.

2. TXRDY is reset when data has been transmitted from TWI_THR to the shift register and set when this data has been 

acknowledged or non acknowledged.

Write THR

Read RHR

SVREAD has to be taken into account only while SVACC is active

TWD

TXRDY

NACK

SVACC

SVREAD

EOSVACC

SADR

S

ADR

R

NA

R

A

DATA

A

A

DATA

NA

S/Sr

DATA

NA

P/S/Sr

SADR matches,

TWI answers with an ACK

SADR does not match,

TWI answers with a NACK

ACK/NACK from the Master