Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
731
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
Reversal of Write to Read
The master initiates the communication by a write command and finishes it by a read command.
describes
the repeated start + reversal from Write to Read mode.
Figure 39-32. Repeated Start + Reversal from Write to Read Mode
Notes: 1. In this case, if TWI_THR has not been written at the end of the read command, the clock is automatically stretched
before the ACK.
2. TXCOMP is only set at the end of the transmission because after the repeated start, SADR is detected again.
39.10.6 Using the DMA Controller
The use of the DMA significantly reduces the CPU load.
To assure correct implementation, respect the following programming sequence.
39.10.6.1 Data Transmit with the DMA
1.
Initialize the DMA (channels, memory pointers, size, etc.).
2.
Configure the slave mode.
3.
Enable the DMA.
4.
Wait for the DMA BTC flag.
5.
Disable the DMA.
6.
(Optional) Wait for the TXCOMP flag in TWI_SR before disabling the peripheral clock if required.
39.10.6.2 Data Receive with the DMA
The DMA transfer size must be defined with the buffer size. In slave mode, the number of characters to receive must be
known in order to configure the DMA.
known in order to configure the DMA.
1.
Initialize the DMA (channels, memory pointers, size, etc.).
2.
Configure the slave mode.
3.
Enable the DMA.
4.
Wait for the DMA BTC flag.
5.
Disable the DMA.
6.
(Optional) Wait for the TXCOMP flag in TWI_SR before disabling the peripheral clock if required.
S
SADR
W
A
DATA0
A
DATA1
SADR
Sr
A
R
A
DATA2
A
DATA3
NA
P
Cleared after read
DATA0
DATA2
DATA3
DATA1
TXCOMP
TXRDY
RXRDY
As soon as a START is detected
Read TWI_RHR
SVACC
SVREAD
TWD
TWI_RHR
TWI_THR
EOSACC