Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
740
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
39.12.5 TWI Clock Waveform Generator Register
Name:
TWI_CWGR
Addresses:
0xF8010010 (0), 0xF8014010 (1)
Access:
Read-write
Reset:
0x00000000
This register can only be written if the WPEN bit is cleared in the
.
TWI_CWGR is only used in Master mode.
• CLDIV: Clock Low Divider
The SCL low period is defined as follows:
• CHDIV: Clock High Divider
The SCL high period is defined as follows:
• CKDIV: Clock Divider
The CKDIV is used to increase both SCL high and low periods.
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
CKDIV
15
14
13
12
11
10
9
8
CHDIV
7
6
5
4
3
2
1
0
CLDIV
t
low
CLDIV
(
2
CKDIV
×
(
)
4
)
+
t
MCK
×
=
t
high
CHDIV
(
2
CKDIV
×
(
)
4
)
+
t
MCK
×
=