Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

Product codes
AT91SAM9N12-EK
Page of 1104
755
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
40.5
I/O Lines Description
40.6
Product Dependencies
40.6.1 I/O 
Lines
The pins used for interfacing the USART may be multiplexed with the PIO lines. The programmer must first program the
PIO controller to assign the desired USART pins to their peripheral function. If I/O lines of the USART are not used by the
application, they can be used for other purposes by the PIO Controller.
To prevent the TXD line from falling when the USART is disabled, the use of an internal pull up is mandatory. If the
hardware handshaking feature  is used, the internal pull up on TXD must also be enabled.
Table 40-1. I/O Line Description
Name
Description
Type
Active Level
SCK
Serial Clock
I/O
TXD
Transmit Serial Data
or Master Out Slave In (MOSI) in SPI Master Mode
or Master In Slave Out (MISO) in SPI Slave Mode
I/O
RXD
Receive Serial Data
or Master In Slave Out (MISO) in SPI Master Mode
or Master Out Slave In (MOSI) in SPI Slave Mode
Input
CTS
Clear to Send
or Slave Select (NSS) in SPI Slave Mode
Input
Low
RTS
Request to Send
or Slave Select (NSS) in SPI Master Mode
Output
Low
Table 40-2. I/O Lines
Instance
Signal
I/O Line
Peripheral
USART0
CTS0
PA3
A
USART0
RTS0
PA2
A
USART0
RXD0
PA1
A
USART0
SCK0
PA4
A
USART0
TXD0
PA0
A
USART1
CTS1
PC28
C
USART1
RTS1
PC27
C
USART1
RXD1
PA6
A
USART1
SCK1
PC29
C
USART1
TXD1
PA5
A
USART2
CTS2
PB1
B
USART2
RTS2
PB0
B
USART2
RXD2
PA8
A
USART2
SCK2
PB2
B
USART2
TXD2
PA7
A