Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
762
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
40.7.2 Receiver and Transmitter Control
After reset, the receiver is disabled. The user must enable the receiver by setting the RXEN bit in the Control Register
(US_CR). However, the receiver registers can be programmed before the receiver clock is enabled.
(US_CR). However, the receiver registers can be programmed before the receiver clock is enabled.
After reset, the transmitter is disabled. The user must enable it by setting the TXEN bit in the US_CR. However, the
transmitter registers can be programmed before being enabled.
transmitter registers can be programmed before being enabled.
The Receiver and the Transmitter can be enabled together or independently.
At any time, the software can perform a reset on the receiver or the transmitter of the USART by setting the
corresponding bit, RSTRX and RSTTX respectively, in the US_CR. The software resets clear the status flag and reset
internal state machines but the user interface configuration registers hold the value configured prior to software reset.
Regardless of what the receiver or the transmitter is performing, the communication is immediately stopped.
corresponding bit, RSTRX and RSTTX respectively, in the US_CR. The software resets clear the status flag and reset
internal state machines but the user interface configuration registers hold the value configured prior to software reset.
Regardless of what the receiver or the transmitter is performing, the communication is immediately stopped.
The user can also independently disable the receiver or the transmitter by setting RXDIS and TXDIS respectively in the
US_CR. If the receiver is disabled during a character reception, the USART waits until the end of reception of the current
character, then the reception is stopped. If the transmitter is disabled while it is operating, the USART waits the end of
transmission of both the current character and character being stored in the Transmit Holding Register (US_THR). If a
timeguard is programmed, it is handled normally.
US_CR. If the receiver is disabled during a character reception, the USART waits until the end of reception of the current
character, then the reception is stopped. If the transmitter is disabled while it is operating, the USART waits the end of
transmission of both the current character and character being stored in the Transmit Holding Register (US_THR). If a
timeguard is programmed, it is handled normally.
40.7.3 Synchronous and Asynchronous Modes
40.7.3.1 Transmitter Operations
The transmitter performs the same in both synchronous and asynchronous operating modes (SYNC = 0 or SYNC = 1).
One start bit, up to 9 data bits, one optional parity bit and up to two stop bits are successively shifted out on the TXD pin
at each falling edge of the programmed serial clock.
One start bit, up to 9 data bits, one optional parity bit and up to two stop bits are successively shifted out on the TXD pin
at each falling edge of the programmed serial clock.
The number of data bits is selected by the CHRL field and the MODE 9 bit in the Mode Register (US_MR). Nine bits are
selected by setting the MODE 9 bit regardless of the CHRL field. The parity bit is set according to the PAR field in
US_MR. The even, odd, space, marked or none parity bit can be configured. The MSBF field in the US_MR configures
which data bit is sent first. If written to 1, the most significant bit is sent first. If written to 0, the less significant bit is sent
first. The number of stop bits is selected by the NBSTOP field in the US_MR. The 1.5 stop bit is supported in
asynchronous mode only.
selected by setting the MODE 9 bit regardless of the CHRL field. The parity bit is set according to the PAR field in
US_MR. The even, odd, space, marked or none parity bit can be configured. The MSBF field in the US_MR configures
which data bit is sent first. If written to 1, the most significant bit is sent first. If written to 0, the less significant bit is sent
first. The number of stop bits is selected by the NBSTOP field in the US_MR. The 1.5 stop bit is supported in
asynchronous mode only.
Figure 40-6. Character Transmit
The characters are sent by writing in the Transmit Holding Register (US_THR). The transmitter reports two status bits in
the Channel Status Register (US_CSR): TXRDY (Transmitter Ready), which indicates that US_THR is empty and
TXEMPTY, which indicates that all the characters written in US_THR have been processed. When the current character
processing is completed, the last character written in US_THR is transferred into the Shift Register of the transmitter and
US_THR becomes empty, thus TXRDY rises.
the Channel Status Register (US_CSR): TXRDY (Transmitter Ready), which indicates that US_THR is empty and
TXEMPTY, which indicates that all the characters written in US_THR have been processed. When the current character
processing is completed, the last character written in US_THR is transferred into the Shift Register of the transmitter and
US_THR becomes empty, thus TXRDY rises.
Both TXRDY and TXEMPTY bits are low when the transmitter is disabled. Writing a character in US_THR while TXRDY
is low has no effect and the written character is lost.
is low has no effect and the written character is lost.
D0
D1
D2
D3
D4
D5
D6
D7
TXD
Start
Bit
Parity
Bit
Stop
Bit
Example: 8-bit, Parity Enabled One Stop
Baud Rate
Clock