Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

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SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

The receiver detects a break condition when all data, parity and stop bits are low. This corresponds to detecting a
framing error with data to 0x00, but FRAME remains low. 

When the low stop bit is detected, the receiver asserts the RXBRK bit in US_CSR. This bit may be cleared by writing the
Control Register (US_CR) with the bit RSTSTA to 1.

An end of receive break is detected by a high level for at least 2/16 of a bit period in asynchronous operating mode or one
sample at high level in synchronous operating mode. The end of break detection also asserts the RXBRK bit.

The USART features a hardware handshaking out-of-band flow control. The RTS and CTS pins are used to connect with
the remote device, as shown in 

. 

Setting the USART to operate with hardware handshaking is performed by writing the USART_MODE field in the Mode
Register (US_MR) to the value 0x2. 

The USART behavior when hardware handshaking is enabled is the same as the behavior in standard synchronous or
asynchronous mode, except that the receiver drives the RTS pin as described below and the level on the CTS pin
modifies the behavior of the transmitter as described below. Using this mode requires using the DMAC channel for
reception. The transmitter can handle hardware handshaking in any case.

 shows how the transmitter operates if hardware handshaking is enabled. The CTS pin disables the

transmitter. If a character is being processing, the transmitter is disabled only after the completion of the current
character and transmission of the next character happens as soon as the pin CTS falls.

D0

D1

D2

D3

D4

D5

D6

D7

TXD

Start 

Bit

Parity

Bit

Stop

Bit

Baud Rate

 Clock

Write

US_CR

TXRDY

TXEMPTY

STPBRK = 1

STTBRK = 1 

Break Transmission

End of Break

USART

TXD

CTS

Remote 

Device

RXD

TXD

RXD

RTS

RTS

CTS