Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

788

SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

The synchronization is done only in Slave node configuration. The procedure is based on time measurement between
falling edges of the Synch Field. The falling edges are available in distances of 2, 4, 6 and 8 bit times.

The time measurement is made by a 19-bit counter clocked by the sampling clock (see 

When the start bit of the Synch Field is detected, the counter is reset. Then during the next 8 Tbits of the Synch Field, the
counter is incremented. At the end of these 8 Tbits, the counter is stopped. At this moment, the 16 most significant bits of
the counter (value divided by 8) give the new clock divider (LINCD) and the 3 least significant bits of this value (the
remainder) give the new fractional part (LINFP). 

When the Synch Field has been received, the clock divider (CD) and the fractional part (FP) are updated in the Baud
Rate Generator register (US_BRGR).

If it appears that the sampled Synch character is not equal to 0x55, then the error flag LINISFE in the Channel Status
register (US_CSR) is set to 1. It is reset by writing bit RSTSTA to 1 in the Control register (US_CR).

RXD

Baud Rate

 Clock

Write RSTSTA=1

in US_CR

LINID

US_LINIR

LINBK

Start

Bit

1

0

1

0

1

0

1

0

Stop

Bit

Start

Bit

ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7

Break Field

13 dominant bits (at 0)

Stop

Bit

Break

Delimiter

1 recessive bit

(at 1)

Synch Byte = 0x55

Start

bit

Stop

bit

Synch Field

8 Tbit

2 Tbit

2 Tbit

2 Tbit

2 Tbit