Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

Product codes
AT91SAM9N12-EK
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SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
40.7.8.11 Response Data Length
The LIN response data length is the number of data fields (bytes) of the response excluding the checksum.
The response data length can either be configured by the user or be defined automatically by bits 4 and 5 of the Identifier
(compatibility to LIN Specification 1.1). The user can choose between these two modes by the DLM bit of the LIN Mode
register (US_LINMR):
DLM = 0: The response data length is configured by the user via the DLC field of the US_LINMR. The response 
data length is equal to (DLC + 1) bytes. DLC can be programmed from 0 to 255, so the response can contain from 
1 data byte up to 256 data bytes.
DLM = 1: The response data length is defined by the Identifier (IDCHR in US_LINIR) according to the table below. 
The DLC field of the US_LINMR is discarded. The response can contain 2 or 4 or 8 data bytes.
Figure 40-43. Response Data Length
40.7.8.12 Checksum
The last field of a frame is the checksum. The checksum contains the inverted 8- bit sum with carry, over all data bytes or
all data bytes and the protected identifier. Checksum calculation over the data bytes only is called classic checksum and
it is used for communication with LIN 1.3 slaves. Checksum calculation over the data bytes and the protected identifier
byte is called enhanced checksum and it is used for communication with LIN 2.0 slaves.
The USART can be configured to:
Send/Check an Enhanced checksum automatically (CHKDIS = 0 & CHKTYP = 0)
Send/Check a Classic checksum automatically (CHKDIS = 0 & CHKTYP = 1)
Not send/check a checksum (CHKDIS = 1)
This configuration is made by the Checksum Type (CHKTYP) and Checksum Disable (CHKDIS) fields of the LIN Mode
register (US_LINMR).
If the checksum feature is disabled, the user can send it manually all the same, by considering the checksum as a normal
data byte and by adding 1 to the response data length (see 
).
40.7.8.13 Frame Slot Mode
This mode is useful only for Master nodes. It respects the following rule: each frame slot shall be longer than or equal to
TFrame_Maximum.
If the Frame Slot Mode is enabled (FSDIS = 0) and a frame transfer has been completed, the TXRDY flag is set again
only after TFrame_Maximum delay, from the start of frame. So the Master node cannot send a new header if the frame
slot duration of the previous frame is inferior to TFrame_Maximum.
Table 40-15. Response Data Length if DLM = 1
IDCHR[5]
IDCHR[4]
Response Data Length [Bytes]
0
0
2
0
1
2
1
0
4
1
1
8
User configuration: 1 - 256 data fields (DLC+1)
Identifier configuration: 2/4/8 data fields
Sync
Break
Sync
Field
Identifier
Field
Checksum
Field
Data
Field
Data
Field
Data
Field
Data
Field