Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

Product codes
AT91SAM9N12-EK
Page of 1104
797
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
40.7.8.16 LIN Frame Handling With the DMAC
The USART can be used in association with the DMAC in order to transfer data directly into/from the on- and off-chip
memories without any processor intervention.
The DMAC uses the trigger flags, TXRDY and RXRDY, to write or read into the USART. The DMAC always writes in the
Transmit Holding register (US_THR) and it always reads in the Receive Holding register (US_RHR). The size of the data
written or read by the DMAC in the USART is always a byte.
Master Node Configuration
The user can choose between two DMAC modes by the PDCM bit in the LIN Mode register (US_LINMR):
PDCM = 1: the LIN configuration is stored in the WRITE buffer and it is written by the DMAC in the Transmit 
Holding register US_THR (instead of the LIN Mode register US_LINMR). Because the DMAC transfer size is 
limited to a byte, the transfer is split into two accesses. During the first access the bits, NACT, PARDIS, CHKDIS, 
CHKTYP, DLM and FSDIS are written. During the second access the 8-bit DLC field is written.
PDCM = 0: the LIN configuration is not stored in the WRITE buffer and it must be written by the user in the LIN 
Mode register (US_LINMR).
The WRITE buffer also contains the Identifier and the DATA, if the USART sends the response (NACT = PUBLISH).
The READ buffer contains the DATA if the USART receives the response (NACT = SUBSCRIBE).
Figure 40-51. Master Node with DMAC (PDCM = 1)
|
|
|
|
|
|
|
|
NACT
PARDIS
CHKDIS
CHKTYP
DLM
FSDIS
DLC
IDENTIFIER
DATA 0
DATA N
WRITE BUFFER
(Peripheral) DMA
Controller
(Peripheral) DMA
Controller
USART3
LIN CONTROLLER
APB bus
NACT
PARDIS
CHKDIS
CHKTYP
DLM
FSDIS
DLC
IDENTIFIER
DATA 0
DATA N
WRITE BUFFER
RXRDY
TXRDY
TXRDY
USART3
LIN CONTROLLER
APB bus
READ BUFFER
NODE ACTION = PUBLISH
NODE ACTION = SUBSCRIBE