Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
866
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
42.6.4 Conversion
Results
When a conversion is completed, the resulting 10-bit digital value is stored in the Channel Data Register (ADC_CDRx) of
the current channel and in the ADC Last Converted Data Register (ADC_LCDR). By setting the TAG option in the
ADC_EMR, the ADC_LCDR presents the channel number associated to the last converted data in the CHNB field.
the current channel and in the ADC Last Converted Data Register (ADC_LCDR). By setting the TAG option in the
ADC_EMR, the ADC_LCDR presents the channel number associated to the last converted data in the CHNB field.
The channel EOC bit in the Status Register (ADC_SR) is set and the DRDY is set. In the case of a connected DMA
channel, DRDY rising triggers a data request. In any case, either EOC and DRDY can trigger an interrupt.
channel, DRDY rising triggers a data request. In any case, either EOC and DRDY can trigger an interrupt.
Reading one of the ADC_CDR registers clears the corresponding EOC bit. Reading ADC_LCDR clears the DRDY bit.
Figure 42-3. EOCx and DRDY Flag Behavior
If the ADC_CDR is not read before further incoming data is converted, the corresponding Overrun Error (OVREx) flag is
set in the Overrun Status Register (ADC_OVER).
set in the Overrun Status Register (ADC_OVER).
Likewise, new data converted when DRDY is high sets the GOVRE bit (General Overrun Error) in ADC_SR.
The OVREx flag is automatically cleared when ADC_OVER is read, and GOVRE flag is automatically cleared when
ADC_SR is read.
ADC_SR is read.
Read the ADC_CDRx
EOCx
DRDY
Read the ADC_LCDR
CHx
(ADC_CHSR)
(ADC_SR)
(ADC_SR)
Write the ADC_CR
with START = 1
with START = 1
Write the ADC_CR
with START = 1
with START = 1