Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

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SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

The SAM9CN12 embeds a Secure Boot allowing firmware stored in external Non-Volatile Memory to be protected.

The content of the external NVM is encrypted and signed based using a 256-bit AES algorithm. Prior to booting from the
externally stored firmware, the secure boot will authenticate the firmware, decrypt it and store it in on-chip memory.
Access to the on-chip memory is prevented and the maximum size of the firmware should not exceed 24 kB. The
programming of the external memory can only be done by the SAM9CN12 using a unique key stored in the on-chip OTP
memory.

Herewith the software is uniquely linked to each SAM9CN12 device. A direct copy of the NVM memory will not run on
another SAM9CN12 device, improving the firmware protection even further.

For software development the user should use the SAM9CN11 without secure boot and full access to on-chip memory
for debug. Once the firmware development has been completed, the SAM9CN11 should be replaced by the SAM9CN12
and programmed via USB with Secure SAM-BA.

Refer to the Secured Application Note "Secure Boot on SAM9CN12" for more details (NDA required).

The system always boots at address 0x0. To ensure maximum boot possibilities, the memory layout can be changed
thanks to the BMS pin. This allows the user to layout the ROM or an external memory to 0x0. The sampling of the BMS
pin is done at reset.

If BMS is detected at 0, the controller boots on the memory connected to Chip Select 0 of the External Bus Interface.

In this boot mode, the chip starts with its default parameters (all registers in their reset state), including as follows:



 the main clock is the on-chip 12 MHz RC oscillator 



 the Static Memory Controller is configured with its default parameters

The user software in the external memory performs a complete configuration:



Enable the 32,768 Hz oscillator if best accuracy is needed



Program the PMC (main oscillator enable or bypass mode)



Program and start the PLL



Reprogram the SMC setup, cycle, hold, mode timing registers for EBI CS0, to adapt them to the new clock



Switch the system clock to the new value

If BMS is detected at 1, the boot memory is the embedded ROM and the Boot Program described below is executed.
(

) 

The ROM Code is a boot program contained in the embedded ROM. It is also called “First level bootloader”.

The ROM Code performs several steps:



basic chip initialization: XTal or external clock frequency detection



attempt to retrieve a valid code from external non-volatile memories (NVM)



execution of a monitor called SAM-BA

®

 Monitor, in case no valid application has been found on any NVM