Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
925
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
43.7.8 Loop
Mode
The receiver can be programmed to receive transmissions from the transmitter. This is done by setting the Loop Mode
(LOOP) bit in SSC_RFMR. In this case, RD is connected to TD, RF is connected to TF and RK is connected to TK.
(LOOP) bit in SSC_RFMR. In this case, RD is connected to TD, RF is connected to TF and RK is connected to TK.
43.7.9 Interrupt
Most bits in SSC_SR have a corresponding bit in interrupt management registers.
The SSC can be programmed to generate an interrupt when it detects an event. The interrupt is controlled by writing
SSC_IER (Interrupt Enable Register) and SSC_IDR (Interrupt Disable Register) These registers enable and disable,
respectively, the corresponding interrupt by setting and clearing the corresponding bit in SSC_IMR (Interrupt Mask
Register), which controls the generation of interrupts by asserting the SSC interrupt line connected to the interrupt
controller.
SSC_IER (Interrupt Enable Register) and SSC_IDR (Interrupt Disable Register) These registers enable and disable,
respectively, the corresponding interrupt by setting and clearing the corresponding bit in SSC_IMR (Interrupt Mask
Register), which controls the generation of interrupts by asserting the SSC interrupt line connected to the interrupt
controller.
Figure 43-16. Interrupt Block Diagram
SSC_IMR
Interrupt
Control
SSC Interrupt
Set
RXRDY
OVRUN
RXSYNC
Receiver
Transmitter
TXRDY
TXEMPTY
TXSYNC
Clear
SSC_IER
SSC_IDR