Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

938

SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

SSC_TFMR

0xF001001C

Read-write  

This register can only be written if the WPEN bit is cleared in 

.

0 = Forbidden value (1-bit data length not supported). 

Any other value: The bit stream contains DATLEN + 1 data bits. .

This bit defines the level driven on the TD pin while out of transmission. Note that if the pin is defined as multi-drive by the PIO 
Controller, the pin is enabled only if the SCC TD output is 1.

0 = The lowest significant bit of the data register is shifted out first in the bit stream.

1 = The most significant bit of the data register is shifted out first in the bit stream.

This field defines the number of data words to be transferred after each transfer start, which is equal to (DATNB +1).

This field defines the length of the Transmit Frame Sync signal and the number of bits shifted out from the Transmit Sync Data 
Register if FSDEN is 1. 

This field is used with FSLEN_EXT to determine the pulse length of the Transmit Frame Sync signal. 

Pulse length is equal to FSLEN + (FSLEN_EXT * 16) + 1 Transmit Clock period. 

31

30

29

28

27

26

25

24

FSLEN_EXT

–

–

–

FSEDGE

23

22

21

20

19

18

17

16

FSDEN

FSOS

FSLEN

15

14

13

12

11

10

9

8

–

–

–

–

DATNB

7

6

5

4

3

2

1

0

MSBF

–

DATDEF

DATLEN

0

NONE

None, RF pin is an input

1

NEGATIVE

Negative Pulse, RF pin is an output

2

POSITIVE

Positive Pulse, RF pin is an output

3

LOW

Driven Low during data transfer

4

HIGH

Driven High during data transfer

5

TOGGLING

Toggling at each start of data transfer