Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

Product codes
AT91SAM9N12-EK
Page of 1104
954
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
44.3
Block Diagram
Figure 44-1.  Block Diagram
32-bit
AHB
Master
Interface
DEAG
Unit
SYSCTRL
Unit
32-bit
APB Interface
Configuration
Registers
Base
Layer
CLUT
LTE
Unit
LCD_DAT[23:0]
LCD_VSYNC
LCD_HSYNC
LCD_PCLK
LCD_DEN
LCD_PWM
LCD_DISP
DEAG: DMA Engine Address Generation
LTE: LCD Timing Engine
AHB
Bus