Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
976
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
44.7.6 LCD Controller Configuration Register 5
Name:
LCDC_LCDCFG5
Address:
0xF8038014
Access:
Read-write
Reset:
0x00000000
• HSPOL: Horizontal Synchronization Pulse Polarity
0: Active High
1: Active Low
• VSPOL: Vertical Synchronization Pulse Polarity
0: Active High
1: Active Low
• VSPDLYS: Vertical Synchronization Pulse Start
0: The first active edge of the Vertical synchronization pulse is synchronous with the second edge of the horizontal pulse.
1: The first active edge of the Vertical synchronization pulse is synchronous with the first edge of the horizontal pulse.
• VSPDLYE: Vertical Synchronization Pulse End
0: The second active edge of the Vertical synchronization pulse is synchronous with the second edge of the horizontal pulse.
1: The second active edge of the Vertical synchronization pulse is synchronous with the first edge of the horizontal pulse.
• DISPPOL: Display Signal Polarity
0: Active High
1: Active Low
• DITHER: LCD Controller Dithering
0: Dithering logical unit is disabled.
1: Dithering logical unit is activated.
• DISPDLY: LCD Controller Display Power Signal Synchronization
0: The LCD_DISP signal is asserted synchronously with the second active edge of the horizontal pulse.
1: The LCD_DISP signal is asserted asynchronously with both edges of the horizontal pulse.
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
GUARDTIME
15
14
13
12
11
10
9
8
–
–
VSPHO
VSPSU
–
–
MODE
7
6
5
4
3
2
1
0
DISPDLY
DITHER
–
DISPPOL
VSPDLYE
VSPDLYS
VSPOL
HSPOL