Atmel Evaluation Kit AT91SAM9X25-EK AT91SAM9X25-EK Data Sheet
Product codes
AT91SAM9X25-EK
176
SAM9X25 [DATASHEET]
11054E–ATARM–10-Mar-2014
21.7.1 Divider and Phase Lock Loop Programming
The divider can be set between 1 and 255 in steps of 1. When a divider field (DIV) is set to 0, the output of the
corresponding divider and the PLL output is a continuous signal at level 0. On reset, each DIV field is set to 0, thus the
corresponding PLL input clock is set to 0.
corresponding divider and the PLL output is a continuous signal at level 0. On reset, each DIV field is set to 0, thus the
corresponding PLL input clock is set to 0.
The PLLA allows multiplication of the divider’s outputs. The PLLA clock signal has a frequency that depends on the
respective source signal frequency and on the parameters DIVA and MULA. The factor applied to the source signal
frequency is (MULA + 1)/DIVA. When MULA is written to 0, the PLLA is disabled and its power consumption is saved.
Re-enabling the PLLA can be performed by writing a value higher than 0 in the MUL field.
respective source signal frequency and on the parameters DIVA and MULA. The factor applied to the source signal
frequency is (MULA + 1)/DIVA. When MULA is written to 0, the PLLA is disabled and its power consumption is saved.
Re-enabling the PLLA can be performed by writing a value higher than 0 in the MUL field.
Whenever the PLLA is re-enabled or one of its parameters is changed, the LOCKA bit in PMC_SR is automatically
cleared. The values written in the PLLACOUNT field in CKGR_PLLAR are loaded in the PLLA counter. The PLLA
counter then decrements at the speed of the Slow Clock until it reaches 0. At this time, the LOCK bit is set in PMC_SR
and can trigger an interrupt to the processor. The user has to load the number of Slow Clock cycles required to cover the
PLLA transient time into the PLLACOUNT field.
cleared. The values written in the PLLACOUNT field in CKGR_PLLAR are loaded in the PLLA counter. The PLLA
counter then decrements at the speed of the Slow Clock until it reaches 0. At this time, the LOCK bit is set in PMC_SR
and can trigger an interrupt to the processor. The user has to load the number of Slow Clock cycles required to cover the
PLLA transient time into the PLLACOUNT field.
The PLLA clock can be divided by 2 by writing the PLLADIV2 bit in PMC_MCKR register.
21.8 UTMI Phase Lock Loop Programming
The source clock of the UTMI PLL is the Main Clock MAINCK. When the 12 MHz Fast RC Oscillator is selected as the
source of MAINCK, the 12 MHz frequency must also be selected because the UTMI PLL multiplier contains a built-in
multiplier of x 40 to obtain the USB High Speed 480 MHz.
source of MAINCK, the 12 MHz frequency must also be selected because the UTMI PLL multiplier contains a built-in
multiplier of x 40 to obtain the USB High Speed 480 MHz.
A 12 MHz crystal is needed to use the USB.
Figure 21-7. UTMI PLL Block Diagram
Whenever the UTMI PLL is enabled by writing UPLLEN in CKGR_UCKR, the LOCKU bit in PMC_SR is automatically
cleared. The values written in the PLLCOUNT field in CKGR_UCKR are loaded in the UTMI PLL counter. The UTMI PLL
counter then decrements at the speed of the Slow Clock divided by 8 until it reaches 0. At this time, the LOCKU bit is set
in PMC_SR and can trigger an interrupt to the processor. The user has to load the number of Slow Clock cycles required
to cover the UTMI PLL transient time into the PLLCOUNT field.
cleared. The values written in the PLLCOUNT field in CKGR_UCKR are loaded in the UTMI PLL counter. The UTMI PLL
counter then decrements at the speed of the Slow Clock divided by 8 until it reaches 0. At this time, the LOCKU bit is set
in PMC_SR and can trigger an interrupt to the processor. The user has to load the number of Slow Clock cycles required
to cover the UTMI PLL transient time into the PLLCOUNT field.
UTMI PLL
UPLLEN
UPLLCOUNT
LOCKU
SLCK
MAINCK
UPLLCK
UTMI PLL
Counter