Atmel Evaluation Kit AT91SAM9X25-EK AT91SAM9X25-EK Data Sheet

178

SAM9X25 [DATASHEET]

11054E–ATARM–10-Mar-2014

The Master Clock Controller provides selection and division of the Master Clock (MCK). MCK is the clock provided to all 
the peripherals and the memory controller. 

The Master Clock is selected from one of the clocks provided by the Clock Generator. Selecting the Slow Clock provides 
a Slow Clock signal to the whole device. Selecting the Main Clock saves power consumption of the PLLs.

The Master Clock Controller is made up of a clock selector and a prescaler. It also contains a Master Clock divider which 
allows the processor clock to be faster than the Master Clock.

The Master Clock selection is made by writing the CSS field (Clock Source Selection) in PMC_MCKR (Master Clock 
Register). The prescaler supports the division by a power of 2 of the selected clock between 1 and 64, and the division by 
3. The PRES field in PMC_MCKR programs the prescaler. 

Each time PMC_MCKR is written to define a new Master Clock, the MCKRDY bit is cleared in PMC_SR. It reads 0 until 
the Master Clock is established. Then, the MCKRDY bit is set and can trigger an interrupt to the processor. This feature 
is useful when switching from a high-speed clock to a lower one to inform the software when the change is actually done.

SLCK

Master Clock 

Prescaler

MCK

PRES

CSS

MAINCK

PLLACK

UPLLCK

To the Processor 
Clock Controller (PCK)

PMC_MCKR

PMC_MCKR