Atmel Evaluation Kit AT91SAM9X25-EK AT91SAM9X25-EK Data Sheet

Product codes
AT91SAM9X25-EK
Page of 1151
179
SAM9X25 [DATASHEET]
11054E–ATARM–10-Mar-2014
22.4 Block Diagram
Figure 22-2. General Clock Block Diagram
22.5 Processor Clock Controller
The PMC features a Processor Clock Controller (PCK) that implements the Processor Idle Mode. The Processor Clock 
can be disabled by writing the System Clock Disable Register (PMC_SCDR). The status of this clock (at least for debug 
purpose) can be read in the System Clock Status Register (PMC_SCSR).
The Processor Clock PCK is enabled after a reset and is automatically re-enabled by any enabled interrupt. The 
Processor Idle Mode is achieved by disabling the Processor Clock and entering Wait for Interrupt Mode. The Processor 
Clock is automatically re-enabled by any enabled fast or normal interrupt, or by reset of the product.
Note: The ARM Wait for Interrupt mode is entered by means of CP15 coprocessor operation. Refer to the Atmel 
application note, 
Optimizing Power Consumption for AT91SAM9261-based Systems
, lit. number 6217.
When the Processor Clock is disabled, the current instruction is finished before the clock is stopped, but this does not 
prevent data transfers from other masters of the system bus. 
UHP48M
UHP12M
MCK 
int
PCK
/1   /2    /3    /4
pck[..]
ON/OFF
USB
 OHCI
USBDIV+1
/4
USB
 EHCI
USBS
Divider
X   /1  /1.5  /2
Divider
PLLACK
UPLLCK
UPLLCK
SLCK
MAINCK
SLCK
MAINCK
Master Clock Controller
2x MCK
Programmable Clock Controller
Periph_clk[..]
Prescaler
/1,/2,/4,...,/64
Prescaler
/1,/2,/3,/4,...,/64
Peripherals
Clock Controller
ON/OFF
Processor
Clock
Controller
DDRCK
/2