Atmel Evaluation Kit AT91SAM9X25-EK AT91SAM9X25-EK Data Sheet
Product codes
AT91SAM9X25-EK
39
SAM9X25 [DATASHEET]
11054E–ATARM–10-Mar-2014
9.6
Memory Management Unit (MMU)
The ARM926EJ-S processor implements an enhanced ARM architecture v5 MMU to provide virtual memory features
required by operating systems like Symbian OS, WindowsCE, and Linux. These virtual memory features are memory
access permission controls and virtual to physical address translations.
required by operating systems like Symbian OS, WindowsCE, and Linux. These virtual memory features are memory
access permission controls and virtual to physical address translations.
The Virtual Address generated by the CPU core is converted to a Modified Virtual Address (MVA) by the FCSE (Fast
Context Switch Extension) using the value in CP15 register13. The MMU translates modified virtual addresses to
physical addresses by using a single, two-level page table set stored in physical memory. Each entry in the set contains
the access permissions and the physical address that correspond to the virtual address.
Context Switch Extension) using the value in CP15 register13. The MMU translates modified virtual addresses to
physical addresses by using a single, two-level page table set stored in physical memory. Each entry in the set contains
the access permissions and the physical address that correspond to the virtual address.
The first level translation tables contain 4096 entries indexed by bits [31:20] of the MVA. These entries contain a pointer
to either a 1 MB section of physical memory along with attribute information (access permissions, domain, etc.) or an
entry in the second level translation tables; coarse table and fine table.
to either a 1 MB section of physical memory along with attribute information (access permissions, domain, etc.) or an
entry in the second level translation tables; coarse table and fine table.
The second level translation tables contain two subtables, coarse table and fine table. An entry in the coarse table
contains a pointer to both large pages and small pages along with access permissions. An entry in the fine table contains
a pointer to large, small and tiny pages.
contains a pointer to both large pages and small pages along with access permissions. An entry in the fine table contains
a pointer to large, small and tiny pages.
Table 7 shows the different attributes of each page in the physical memory.
The MMU consists of:
Access control logic
Translation Look-aside Buffer (TLB)
Translation table walk hardware
9.6.1
Access Control Logic
The access control logic controls access information for every entry in the translation table. The access control logic
checks two pieces of access information: domain and access permissions. The domain is the primary access control
mechanism for a memory region; there are 16 of them. It defines the conditions necessary for an access to proceed. The
domain determines whether the access permissions are used to qualify the access or whether they should be ignored.
checks two pieces of access information: domain and access permissions. The domain is the primary access control
mechanism for a memory region; there are 16 of them. It defines the conditions necessary for an access to proceed. The
domain determines whether the access permissions are used to qualify the access or whether they should be ignored.
The second access control mechanism is access permissions that are defined for sections and for large, small and tiny
pages. Sections and tiny pages have a single set of access permissions whereas large and small pages can be
associated with 4 sets of access permissions, one for each subpage (quarter of a page).
pages. Sections and tiny pages have a single set of access permissions whereas large and small pages can be
associated with 4 sets of access permissions, one for each subpage (quarter of a page).
9.6.2
Translation Look-aside Buffer (TLB)
The Translation Look-aside Buffer (TLB) caches translated entries and thus avoids going through the translation process
every time. When the TLB contains an entry for the MVA (Modified Virtual Address), the access control logic determines
if the access is permitted and outputs the appropriate physical address corresponding to the MVA. If access is not
permitted, the MMU signals the CPU core to abort.
every time. When the TLB contains an entry for the MVA (Modified Virtual Address), the access control logic determines
if the access is permitted and outputs the appropriate physical address corresponding to the MVA. If access is not
permitted, the MMU signals the CPU core to abort.
If the TLB does not contain an entry for the MVA, the translation table walk hardware is invoked to retrieve the translation
information from the translation table in physical memory.
information from the translation table in physical memory.
Table 9-6.
Mapping Details
Mapping Name
Mapping Size
Access Permission By
Subpage Size
Section
1M byte
Section
-
Large Page
64K bytes
4 separated subpages
16K bytes
Small Page
4K bytes
4 separated subpages
1K byte
Tiny Page
1K byte
Tiny Page
-