Atmel Evaluation Kit AT91SAM9X25-EK AT91SAM9X25-EK Data Sheet

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SAM9X25 [DATASHEET]

11054E–ATARM–10-Mar-2014

The translation table walk hardware is a logic that traverses the translation tables located in physical memory, gets the 
physical address and access permissions and updates the TLB.

The number of stages in the hardware table walking is one or two depending whether the address is marked as a 
section-mapped access or a page-mapped access.

There are three sizes of page-mapped accesses and one size of section-mapped access. Page-mapped accesses are 
for large pages, small pages and tiny pages. The translation process always begins with a level one fetch. A section-
mapped access requires only a level one fetch, but a page-mapped access requires an additional level two fetch. For 
further details on the MMU, please refer to chapter 3 in ARM926EJ-S Technical Reference Manual.

The MMU generates an abort on the following types of faults:



Alignment faults (for data accesses only)



Translation faults



Domain faults



Permission faults

The access control mechanism of the MMU detects the conditions that produce these faults. If the fault is a result of 
memory access, the MMU aborts the access and signals the fault to the CPU core.The MMU retains status and address 
information about faults generated by the data accesses in the data fault status register and fault address register. It also 
retains the status of faults generated by instruction fetches in the instruction fault status register.

The fault status register (register 5 in CP15) indicates the cause of a data or prefetch abort, and the domain number of 
the aborted access when it happens. The fault address register (register 6 in CP15) holds the MVA associated with the 
access that caused the Data Abort. For further details on MMU faults, please refer to chapter 3 in ARM926EJ-S 
Technical Reference Manual.

The ARM926EJ-S contains a 16KB Instruction Cache (ICache), a 16KB Data Cache (DCache), and a write buffer. 
Although the ICache and DCache share common features, each still has some specific mechanisms.

The caches (ICache and DCache) are four-way set associative, addressed, indexed and tagged using the Modified 
Virtual Address (MVA), with a cache line length of eight words with two dirty bits for the DCache. The ICache and 
DCache provide mechanisms for cache lockdown, cache pollution control, and line replacement.

A new feature is now supported by ARM926EJ-S caches called allocate on read-miss commonly known as wrapping. 
This feature enables the caches to perform critical word first cache refilling. This means that when a request for a word 
causes a read-miss, the cache performs an AHB access. Instead of loading the whole line (eight words), the cache loads 
the critical word first, so the processor can reach it quickly, and then the remaining words, no matter where the word is 
located in the line.

The caches and the write buffer are controlled by the CP15 register 1 (Control), CP15 register 7 (cache operations) and 
CP15 register 9 (cache lockdown).

The ICache caches fetched instructions to be executed by the processor. The ICache can be enabled by writing 1 to I bit 
of the CP15 Register 1 and disabled by writing 0 to this same bit.

When the MMU is enabled, all instruction fetches are subject to translation and permission checks. If the MMU is 
disabled, all instructions fetches are cachable, no protection checks are made and the physical address is flat-mapped to 
the modified virtual address. With the MVA use disabled, context switching incurs ICache cleaning and/or invalidating.

When the ICache is disabled, all instruction fetches appear on external memory (AHB) (see Tables 4-1 and 4-2 in page 
4-4 in ARM926EJ-S TRM).