Atmel Evaluation Kit AT91SAM9X25-EK AT91SAM9X25-EK Data Sheet
Product codes
AT91SAM9X25-EK
539
SAM9X25 [DATASHEET]
11054E–ATARM–10-Mar-2014
32.6.8 Transfer With DMA
USB packets of any length may be transferred when required by the UDPHS Device. These transfers always feature
sequential addressing.
sequential addressing.
Packet data AHB bursts may be locked on a DMA buffer basis for drastic overall AHB bus bandwidth performance boost
with paged memories. These clock-cycle consuming memory row (or bank) changes will then likely not occur, or occur
only once instead of dozens times, during a single big USB packet DMA transfer in case another AHB master addresses
the memory. This means up to 128-word single-cycle unbroken AHB bursts for Bulk endpoints and 256-word single-cycle
unbroken bursts for isochronous endpoints. This maximum burst length is then controlled by the lowest programmed
USB endpoint size (EPT_SIZE field in the UDPHS_EPTCFGx register) and DMA Size (BUFF_LENGTH field in the
UDPHS_DMACONTROLx register).
with paged memories. These clock-cycle consuming memory row (or bank) changes will then likely not occur, or occur
only once instead of dozens times, during a single big USB packet DMA transfer in case another AHB master addresses
the memory. This means up to 128-word single-cycle unbroken AHB bursts for Bulk endpoints and 256-word single-cycle
unbroken bursts for isochronous endpoints. This maximum burst length is then controlled by the lowest programmed
USB endpoint size (EPT_SIZE field in the UDPHS_EPTCFGx register) and DMA Size (BUFF_LENGTH field in the
UDPHS_DMACONTROLx register).
The USB 2.0 device average throughput may be up to nearly 60 MBytes. Its internal slave average access latency
decreases as burst length increases due to the 0 wait-state side effect of unchanged endpoints. If at least 0 wait-state
word burst capability is also provided by the external DMA AHB bus slaves, each of both DMA AHB busses need less
than 50% bandwidth allocation for full USB 2.0 bandwidth usage at 30 MHz, and less than 25% at 60 MHz.
decreases as burst length increases due to the 0 wait-state side effect of unchanged endpoints. If at least 0 wait-state
word burst capability is also provided by the external DMA AHB bus slaves, each of both DMA AHB busses need less
than 50% bandwidth allocation for full USB 2.0 bandwidth usage at 30 MHz, and less than 25% at 60 MHz.
The UDPHS DMA Channel Transfer Descriptor is described in
.
Note:
In case of debug, be careful to address the DMA to an SRAM address even if a remap is done.
Figure 32-7. Example of DMA Chained List
32.6.9 Transfer Without DMA
Important. If the DMA is not to be used, it is necessary that it be disabled because otherwise it can be enabled by
previous versions of software without warning. If this should occur, the DMA can process data before an interrupt
without knowledge of the user.
previous versions of software without warning. If this should occur, the DMA can process data before an interrupt
without knowledge of the user.
The recommended means to disable DMA is as follows:
// Reset IP UDPHS
AT91C_BASE_UDPHS->UDPHS_CTRL &= ~AT91C_UDPHS_EN_UDPHS;
AT91C_BASE_UDPHS->UDPHS_CTRL |= AT91C_UDPHS_EN_UDPHS;
// With OR without DMA !!!
Data Buff 1
Data Buff 2
Data Buff 3
Memory Area
Transfer Descriptor
Next Descriptor Address
DMA Channel Address
DMA Channel Control
Transfer Descriptor
Next Descriptor Address
DMA Channel Address
DMA Channel Control
Transfer Descriptor
Next Descriptor Address
DMA Channel Address
DMA Channel Control
UDPHS Registers
(Current Transfer Descriptor)
UDPHS Next Descriptor
DMA Channel Address
DMA Channel Control
Null