Atmel Evaluation Kit AT91SAM9X25-EK AT91SAM9X25-EK Data Sheet
Product codes
AT91SAM9X25-EK
542
SAM9X25 [DATASHEET]
11054E–ATARM–10-Mar-2014
This algorithm must not be used for isochronous transfer. In this case, the ping-pong mechanism does not operate.
A Zero Length Packet can be sent by setting just the TXRDY flag in the UDPHS_EPTSETSTAx register.
32.6.10.6 Bulk IN or Interrupt IN: Sending a Buffer Using DMA (Device to Host)
The UDPHS integrates a DMA host controller. This DMA controller can be used to transfer a buffer from the memory to
the DPR or from the DPR to the processor memory under the UDPHS control. The DMA can be used for all transfer
types except control transfer.
the DPR or from the DPR to the processor memory under the UDPHS control. The DMA can be used for all transfer
types except control transfer.
Example DMA configuration:
1.
Program UDPHS_DMAADDRESS x with the address of the buffer that should be transferred.
2.
Enable the interrupt of the DMA in UDPHS_IEN
3.
Program UDPHS_ DMACONTROLx:
Size of buffer to send: size of the buffer to be sent to the host.
END_B_EN: The endpoint can validate the packet (according to the values programmed in the
AUTO_VALID and SHRT_PCKT fields of UDPHS_EPTCTLx.) (See
AUTO_VALID and SHRT_PCKT fields of UDPHS_EPTCTLx.) (See
END_BUFFIT: generate an interrupt when the BUFF_COUNT in UDPHS_DMASTATUSx reaches 0.
CHANN_ENB: Run and stop at end of buffer
The auto-valid-bank mechanism allows the transfer of data (IN & OUT) without the intervention of the CPU. This means
that bank validation (set TXRDY or clear the RXRDY_TXKL bit) is done by hardware.
that bank validation (set TXRDY or clear the RXRDY_TXKL bit) is done by hardware.
A transfer descriptor can be used. Instead of programming the register directly, a descriptor should be programmed and
the address of this descriptor is then given to UDPHS_DMANXTDSC to be processed after setting the LDNXT_DSC field
(Load Next Descriptor Now) in UDPHS_DMACONTROLx register.
the address of this descriptor is then given to UDPHS_DMANXTDSC to be processed after setting the LDNXT_DSC field
(Load Next Descriptor Now) in UDPHS_DMACONTROLx register.
The structure that defines this transfer descriptor must be aligned.
Each buffer to be transferred must be described by a DMA Transfer descriptor (see
). Transfer descriptors are chained. Before executing transfer of the buffer, the UDPHS may
fetch a new transfer descriptor from the memory address pointed by the UDPHS_DMANXTDSCx register. Once the
transfer is complete, the transfer status is updated in the UDPHS_DMASTATUSx register.
transfer is complete, the transfer status is updated in the UDPHS_DMASTATUSx register.
To chain a new transfer descriptor with the current DMA transfer, the DMA channel must be stopped.
To do so,
INTDIS_DMA and TXRDY may be set in the UDPHS_EPTCTLENBx register.
It is also possible for the application to wait
for the completion of all transfers. In this case the LDNXT_DSC field in the last transfer descriptor
UDPHS_DMACONTROLx register must be set to 0 and CHANN_ENB set to 1.
UDPHS_DMACONTROLx register must be set to 0 and CHANN_ENB set to 1.
Then the application can chain a new transfer descriptor.
The INTDIS_DMA can be used to stop the current DMA transfer if an enabled interrupt is triggered. This can be used to
stop DMA transfers in case of errors.
stop DMA transfers in case of errors.
The application can be notified at the end of any buffer transfer (ENB_BUFFIT bit in the UDPHS_DMACONTROLx
register).
register).