Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet

 1045

SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

The LCD Controller (LCDC) consists of logic for transferring LCD image data from an external display buffer to an
LCD module with integrated common and segment drivers.

The LCD Controller supports single and double scan monochrome and color passive STN LCD modules and single
scan active TFT LCD modules. On monochrome STN displays, up to 16 gray shades are supported using a time-
based dithering algorithm and Frame Rate Control (FRC) method. This method is also used in color STN displays
to generate up to 4096 colors.

The LCD Controller has a display input buffer (FIFO) to allow a flexible connection of the external AHB master
interface, and a lookup table to allow palletized display configurations.

The LCD Controller is programmable in order to support many different requirements such as resolutions up to
2048 x 2048; pixel depth (1, 2, 4, 8, 16, 24 bits per pixel); data line width (4, 8, 16 or 24 bits) and interface timing.

The LCD Controller is connected to the ARM Advanced High Performance Bus (AHB) as a master for reading pixel
data. However, the LCD Controller interfaces with the AHB as a slave in order to configure its registers.

• Single and Dual scan color and monochrome passive STN LCD panels supported

• Single scan active TFT LCD panels supported.

• 4-bit single scan, 8-bit single or dual scan, 16-bit dual scan STN interfaces supported

• Up to 24-bit single scan TFT interfaces supported

• Up to 16 gray levels for mono STN and up to 4096 colors for color STN displays

• 1, 2 bits per pixel (palletized), 4 bits per pixel (non-palletized) for mono STN

• 1, 2, 4, 8 bits per pixel (palletized), 16 bits per pixel (non-palletized) for color STN

• 1, 2, 4, 8 bits per pixel (palletized), 16, 24 bits per pixel (non-palletized) for TFT

• Single clock domain architecture

• Resolution supported up to 2048 x 2048