Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet

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SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

The line counting is controlled by the read-only field LINECNT of LCDCON1 register. The LINECNT field
decreases by one unit at each falling edge of LCDHSYNC. 

This block is used to configure the polarity of the data and control signals. The polarity of all clock signals can be
configured by LCDCON2[12:8] register setting. 

This block also generates the lcd_pwr signal internally used to control the state of the LCD pins and to turn on and
off by software the LCD module.

It is also available on the LCDPWR pin.

This signal is controlled by the PWRCON register and respects the number of frames configured in the
GUARD_TIME field of PWRCON register (PWRCON[7:1]) between the write access to LCD_PWR field (PWR-
CON[0]) and the activation/deactivation of lcd_pwr signal. 

The minimum value for the GUARD_TIME field is one frame. This gives the DMA Controller enough time to fill the
FIFOs before the start of data transfer to the LCD.

This block generates the LCD contrast control signal (LCDCC) to make possible the control of the display's con-
trast by software. This is an 8-bit PWM (Pulse Width Modulation) signal that can be converted to an analog voltage
with a simple passive filter.

The PWM module has a free-running counter whose value is compared against a compare register
(CONSTRAST_VAL register). If the value in the counter is less than that in the register, the output brings the value
of the polarity (POL) bit in the PWM control register: CONTRAST_CTR. Otherwise, the opposite value is output.
Thus, a periodic waveform with a pulse width proportional to the value in the compare register is generated.

Due to the comparison mechanism, the output pulse has a width between zero and 255 PWM counter cycles. Thus
by adding a simple passive filter outside the chip, an analog voltage between 0 and (255/256) × VDD can be
obtained (for the positive polarity case, or between (1/256) × VDD and VDD for the negative polarity case). Other
voltage values can be obtained by adding active external circuitry.

For PWM mode, the frequency of the counter can be adjusted to four different values using field PS of
CONTRAST_CTR register.

The LCD Controller interfaces with the LCD Module through the LCD Interface (

). The

Controller supports the following interface configurations: 24-bit TFT single scan, 16-bit STN Dual Scan Mono
(Color), 8-bit STN Dual (Single) Scan Mono (Color), 4-bit single scan Mono (Color).

A 4-bit single scan STN display uses 4 parallel data lines to shift data to successive single horizontal lines one at a
time until the entire frame has been shifted and transferred. The 4 LSB pins of LCD Data Bus (LCDD [3:0]) can be
directly connected to the LCD driver; the 20 MSB pins (LCDD [23:4]) are not used.

An 8-bit single scan STN display uses 8 parallel data lines to shift data to successive single horizontal lines one at
a time until the entire frame has been shifted and transferred. The 8 LSB pins of LCD Data Bus (LCDD [7:0]) can
be directly connected to the LCD driver; the 16 MSB pins (LCDD [23:8]) are not used.

An 8-bit Dual Scan STN display uses two sets of 4 parallel data lines to shift data to successive upper and lower
panel horizontal lines one at a time until the entire frame has been shifted and transferred. The bus LCDD[3:0] is
connected to the upper panel data lines and the bus LCDD[7:4] is connected to the lower panel data lines. The rest
of the LCD Data Bus lines (LCDD[23:8]) are not used.

A 16-bit Dual Scan STN display uses two sets of 8 parallel data lines to shift data to successive upper and lower
panel horizontal lines one at a time until the entire frame has been shifted and transferred. The bus LCDD[7:0] is