Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet
Product codes
AT91SAM9M10-G45-EK
1084
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
45.12.12 LCD Timing Configuration Register 1
Name:
LCDTIM1
Address:
0x00500808
Access:
Read-write
Reset value:
0x0000000
• VFP: Vertical Front Porch
In TFT mode, these bits equal the number of idle lines at the end of the frame.
In STN mode, these bits should be set to 0.
• VBP: Vertical Back Porch
In TFT mode, these bits equal the number of idle lines at the beginning of the frame.
In STN mode, these bits should be set to 0.
• VPW: Vertical Synchronization pulse width
In TFT mode, these bits equal the vertical synchronization pulse width, given in number of lines. LCDVSYNC width is equal
to (VPW+1) lines.
to (VPW+1) lines.
In STN mode, these bits should be set to 0.
• VHDLY: Vertical to horizontal delay
In TFT mode, this is the delay between LCDVSYNC rising or falling edge and LCDHSYNC rising edge. Delay is
(VHDLY+1) LCDDOTCK cycles. Bit 31 must be written to 1.
(VHDLY+1) LCDDOTCK cycles. Bit 31 must be written to 1.
In STN mode, these bits should be set to 0.
31
30
29
28
27
26
25
24
1
–
–
–
VHDLY
23
22
21
20
19
18
17
16
–
–
VPW
15
14
13
12
11
10
9
8
VBP
7
6
5
4
3
2
1
0
VFP